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| HM5116100 Series 16 M FP DRAM (16-Mword x 1-bit) 4 k Refresh ADE-203-646E (Z) Rev. 5.0 Nov. 1997 Description The Hitachi HM5116100 is a CMOS dynamic RAM organized 16,777,216-word x 1-bit. It employs the most advanced 0.5m CMOS technology for high performance and low power. The HM5116100 offers Fast Page Mode as a high speed access mode. It is packaged in 26-pin plastic SOJ. Features * Single 5 V (10%) * Access time: 60 ns/70 ns (max) * Power dissipation Active mode: 440 mW/385 mW (max) Standby mode 11 mW (max) * Fast page mode capability * Refresh cycles 4096 refresh cycles : 64 ms * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * Test function 16-bit parallel test mode Ordering Information Type No. HM5116100S-6 HM5116100S-7 Access time 60 ns 70 ns Package 300-mil 26-pin plastic SOJ (CP-26/24DB) HM5116100 Series Pin Arrangement HM5116100S Series VCC Din NC WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS Dout NC CAS NC A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name A0 to A11 Function Address input * * Din Dout RAS CAS WE VCC VSS NC Row/Refresh A0 to A11 Column A0 to A11 Data input Data output Row address strobe Column address strobe Read/write enable Power supply Ground No connection 2 HM5116100 Series Block Diagram RAS CAS WE Timing and control A0 A1 to A11 Row decoder * * * Column address buffers Column decoder Din buffer Din * * * 16M array Row address buffers Dout buffer Dout 3 HM5116100 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Note: 1. All voltage referred to VSS Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 4 HM5116100 Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM5116100 -6 Parameter Operating current Standby current *1, *2 -7 Max 80 2 Min -- -- Max 70 2 Unit mA mA Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC - 0.2V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA Symbol I CC1 I CC2 Min -- -- -- 1 -- 1 mA RAS-only refresh current*2 Standby current *1 I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 80 5 80 70 10 10 VCC 0.4 -- -- -- -- -10 -10 2.4 0 70 5 70 60 10 10 VCC 0.4 mA mA mA mA A A V V CAS-before-RAS refresh current Fast page mode current Input leakage current Output leakage current Output high voltage Output low voltage *1, *3 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address, Data-in) Input capacitance (Clocks) Output capacitance (Data-out) Symbol CI1 CI2 CO Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Booton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 5 HM5116100 Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *16 Test Conditions * Input rise and fall time : 5 ns * Input timing reference levels : 0.8 V, 2.4 V * Output load : 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116100 -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP tT Min 110 40 10 60 15 0 10 0 10 20 15 15 60 5 3 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- 50 -7 Min 130 50 10 70 18 0 10 0 15 20 15 18 70 5 3 Max -- -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 3 4 Notes 6 HM5116100 Series Read Cycle HM5116100 -6 Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output buffer turn-off time Symbol t RAC t CAC t AA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OFF Min -- -- -- 0 0 0 30 30 0 3 -- Max 60 15 30 -- -- -- -- -- -- -- 15 -7 Min -- -- -- 0 0 0 35 35 0 3 -- Max 70 18 35 -- -- -- -- -- -- -- 15 Unit ns ns ns ns ns ns ns ns ns ns ns 11 10 10 Notes 6, 7, 17 7, 8, 15, 17 7, 9, 15, 17 Write Cycle HM5116100 -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 13 13 Notes 12 7 HM5116100 Series Read-Modify-Write Cycle HM5116100 -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Symbol t RWC t RWD t CWD t AWD Min 130 60 15 30 Max -- -- -- -- -7 Min 153 70 18 35 Max -- -- -- -- Unit ns ns ns ns 12 12 12 Notes Refresh Cycle HM5116100 -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 5 10 0 10 5 Max -- -- -- -- -- -7 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes Fast Page Mode Cycle HM5116100 -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol t PC t RASP t CPA t CPRH Min 40 -- -- 35 Max -- -7 Min 45 Max -- Unit ns 14 7, 15, 17 Notes 100000 -- 35 -- -- 40 100000 ns 40 -- ns ns 8 HM5116100 Series Fast Page Mode Read-Modify-Write Cycle HM5116100 -6 Parameter Fast page mode read-modify-write cycle time WE delay time from CAS precharge Symbol t PRWC t CPW Min 60 35 Max -- -- -7 Min 68 40 Max -- -- Unit ns ns 12 Notes Test Mode Cycle *16 HM5116100 -6 Parameter Test mode WE setup time Test mode WE hold time Symbol t WTS t WTH Min 0 10 Max -- -- -7 Min 0 10 Max -- -- Unit ns ns Notes Refresh Cycle Parameter Refresh period Symbol t REF Max 64 Unit ms Note 4096 cycles 9 HM5116100 Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. Assume that tRCD tRCD (max) and tRAD tRAD (max). 9. Assume that tRCD tRCD (max) and tRAD tRAD (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD t CWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 13. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 14. t RASP defines RAS pulse width in fast page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0, CA1, CA10 and CA11 for the 16M x 1 are don't care during test mode. Test mode is set by performing a WEand-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 16 bits in parallel at Din and read out from Dout. If 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CASbefore-RAS refresh cycle or RAS-only refresh cycle. 17. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout 10 HM5116100 Series Timing Waveforms*18 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t RAH t ASC t RAL t CAL t CAH Address Row Column t RRH t RCS t RCH WE t CAC t AA t RAC t CLZ Dout Dout t OH t OFF 11 HM5116100 Series Early Write Cycle tRC tRAS tRP RAS tCSH tRCD tT CAS tRSH tCAS tCRP tASR tRAH tASC tCAH Address Row Column tWCS tWCH WE tDS tDH Din Din Dout High-Z* * t WCS t WCS (min) 12 HM5116100 Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t CWL t RWL t RCS t WP WE t DS t DH Din Din t CLZ t OFF Dout Invalid Dout 13 HM5116100 Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row Column t RCS t CWD t AWD t RWD t WP t CWL t RWL WE t DS t DH Din t CAC t AA t RAC t CLZ Dout Din t OH t OFF Dout 14 HM5116100 Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP t ASR t RAH Address Row t OFF Dout High-Z CAS-Before-RAS Refresh Cycle t RC t RC t RP t RAS t RP t RAS t RP RAS t RPC t CP tT t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP t WRH WE Address t OFF Dout High-Z 15 HM5116100 Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RC t RP t RAS t RP t RP RAS tT t RSH t RCD t CHR t CRP CAS t RAD t ASR Address t RAH t ASC t RAL t CAH Column Row t RCS t WRP t RRH t WRH t WRP t WRH WE t CAC t AA t RAC t CLZ Dout Dout t OH t OFF 16 HM5116100 Series Fast Page Mode Read Cycle t RASP t CPRH RAS t RP tT t CSH t RCD CAS t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RAD t ASR t RAH t ASC t CAL t CAH t ASC t CAL t CAH t ASC t RAL t CAL t CAH Address Row Column 1 Column 2 t RCS Column N t RCS tRRH tRCH t RCS t RCH t RCH WE t CAC t AA t RAC t CLZ Dout t OH t OFF t CPA t AA t CAC t CLZ t OH t OFF t CPA t AA t CAC t CLZ t OH t OFF Dout 1 Dout 2 Dout N 17 HM5116100 Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 18 HM5116100 Series Fast Page Mode Delayed Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 t CWL t RCS t WP Column 2 t CWL t RCS t WP Column N t RWL t CWL t RCS t WP WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N t CLZ t OFF t CLZ t OFF t CLZ t OFF Dout Invalid Dout Invalid Dout Invalid Dout 19 HM5116100 Series Fast Page Mode Read-Modify-Write Cycle t RASP t RP RAS tT t RCD t CAS t CP t PRWC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAD t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row t RCS t RWD Column 1 t RCS t AWD t CWL Column 2 t CWL t AWD t WP t WP t CWD Column N t RCS t AWD t WP t CWD t RWL t CWL WE t CWD t DS t DH t CPW t DS t DH t CPW t DS t DH Din Din 1 Din 2 Din N t CAC t CAC t CAC t AA t CPA t AA t CPA t AA t RAC t OH t OH t OH t OFF t CLZ t OFF t CLZ t OFF t CLZ Dout Dout 1 Dout 2 Dout N 20 HM5116100 Series Test Mode Cycle*16 *,** Reset Cycle Set Cycle** Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din: H or L Test Mode Set Cycle t RC t RP t RAS t RP RAS t RPC t CSR tT CAS t CP t WTS t CHR t RPC t CRP t WTH t CP WE Address t OFF Dout High-Z AA @@ A @ 21 HM5116100 Series Package Dimensions HM5116100S Series (CP-26/24DB) Unit: mm 26 16.90 17.27 Max 21 19 14 8.51 0.13 7.62 0.13 1 3.50 0.26 68 0.74 13 2.65 0.12 6.79 - 0.18 + 0.19 1.30 Max 0.43 0.10 0.41 0.08 1.27 2.54 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) CP-26/24DB Conforms Conforms 0.8 g Dimension including the plating thickness Base material dimension 22 0.80 +0.25 -0.17 HM5116100 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 23 HM5116100 Series Revision Record Rev. 1.0 2.0 3.0 4.0 5.0 Date Oct. 14, 1996 Dec. 10, 1996 Feb. 27, 1997 Jun. 24, 1997 Nov. 1997 Contents of Modification Initial issue Addition of HM5116100-5 Series AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Deletion of HM5116100-5 Series Change of Subtitle Drawn by Y. Kasama Y. Kasama Y. Kasama Y. Kasama Approved by M. Mishima Y. Matsuno Y. Matsuno Y. Matsuno 24 |
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